1. Field of the Invention
The present invention relates to row decoders for memory, and more particularly, to a row decoder and related method with reduced program disturb and layout area.
2. Description of the Prior Art
Flash memory is a type of non-volatile memory commonly employed in memory cards, flash drives, and portable electronics for providing data storage and transfer. Flash memory may be electrically written to, erased, and reprogrammed to allow deletion of data and writing of new data. Some advantages of flash memory include fast read access time, and shock resistance. Flash memory is also very resistant to pressure and temperature variations.
Please refer to FIG. 1, which is a diagram of a row driving circuit 10. To program a memory unit of flash memory, an address of the memory unit may be decoded by a decoder to select a memory block comprising the memory unit. The address may be further decoded to determine a word line of the memory unit. The row driving circuit 10 is utilized for driving the memory unit of the memory block to read, write, or erase data from or to the memory unit. The row driving circuit 10 comprises eight NOR gates 100 for receiving a memory block selection signal [XPA, XPB, XPC], eight level shift up circuits 121, eight level shift down circuits 122, eight pull-up transistors MP, eight pull down transistors MN, and eight reset transistors M_RESET. The row driving circuit 10 outputs an eight-bit word line selection signal ZWL<7:0> for selecting the word line of the memory unit to be accessed.
Please refer to FIG. 2, which is a diagram of one of the level shift up circuits 121. Each level shift up circuit 121 may include a first NMOS transistor MN1, a first PMOS transistor MP1, a second NMOS transistor MN2, a second PMOS transistor MP2, and an inverter 200. Input voltage to the level shift up circuit 121 is received at a gate terminal of the first NMOS transistor MN1. The input voltage is also inverted by the inverter 200, and output to a gate terminal of the second NMOS transistor MN2. The first NMOS transistor MN1 and the first PMOS transistor MP1 act as an inverter, and output a first inverted signal to a gate terminal of the second PMOS transistor MP2. Likewise, the second NMOS transistor MN2 and the second PMOS transistor MP2 act as an inverter, and output a second inverted signal to a gate terminal of the first PMOS transistor MP1. Thus, if the input voltage is high, output voltage of the level shift up circuit 121 taken at drains of the second NMOS transistor MN2 and the second PMOS transistor MP2 will be a high voltage VPP. If the input voltage is low, then the output voltage will be a low voltage, such as ground.
Please refer to FIG. 3, which is a diagram of one of the level shift down circuits 122. Each level shift down circuit 122 may include a first NMOS transistor MN1, a first PMOS transistor MP1, a second NMOS transistor MN2, a second PMOS transistor MP2, and an inverter 200. Input voltage to the level shift down circuit 122 is received at a gate terminal of the first PMOS transistor MP1. The input voltage is also inverted by the inverter 200, and output to a gate terminal of the second PMOS transistor MP2. The first NMOS transistor MN1 and the first PMOS transistor MP1 act as an inverter, and output a first inverted signal to a gate terminal of the second NMOS transistor MN2. Likewise, the second NMOS transistor MN2 and the second PMOS transistor MP2 act as an inverter, and output a second inverted signal to a gate terminal of the first NMOS transistor MN1. Thus, if the input voltage is low, output voltage of the level shift down circuit 122 taken at drains of the second NMOS transistor MN2 and the second PMOS transistor MP2 will be a low voltage VBB. If the input voltage is high, then the output voltage will be a high voltage VDD. The high voltage VDD may be equal to or lower than the high voltage VPP.
Two cases exist for the input voltage to the level shift up circuit 121 and the level shift down circuit 122. The input voltage may be high. Thus, the level shift up circuit 121 may output the high voltage VPP to the pull-up transistor MP, and the level shift down circuit 122 may output the high voltage VDD to the pull-down transistor MN. If the input voltage is low, the level shift up circuit 121 may output the low voltage, e.g. ground, and the level shift down circuit 122 may output the low voltage VBB. Thus, the word line selection signal ZWL<7:0> will have seven VPP outputs and one XWV output. For example, the word line selection signal ZWL<1> may have voltage of the signal XWV<1>, and the word line selection signals ZWL<7:2>, ZWL<0> may have voltage of the high voltage VPP. This is shown in FIG. 4. A reset signal ZXWV<7:0> may be utilized to control the reset transistor M_RESET.
The row driving circuit 10 uses the level shift up circuit 121 and the level shift down circuit 122, as well as the pull-up transistor MP, the pull-down transistor MN, and the reset transistor M_RESET. This architecture is complex, and takes more chip area.